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| MCP1727 1.5A, Low Voltage, Low Quiescent Current LDO Regulator Features * * * * * * * * * * * * * * 1.5A Output Current Capability Input Operating Voltage Range: 2.3V to 6.0V Adjustable Output Voltage Range: 0.8V to 5.0V Standard Fixed Output Voltages: - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V Other Fixed Output Voltage Options Available Upon Request Low Dropout Voltage: 330 mV Typical at 1.5A Typical Output Voltage Tolerance: 0.5% Stable with 1.0 F Ceramic Output Capacitor Fast response to Load Transients Low Supply Current: 120 A (typ) Low Shutdown Supply Current: 0.1 A (typ) Adjustable Delay on Power Good Output Short Circuit Current Limiting and Overtemperature Protection 3x3 DFN-8 and SOIC-8 Package Options Description The MCP1727 is a 1.5A Low Dropout (LDO) linear regulator that provides high current and low output voltages in a very small package. The MCP1727 comes in a fixed (or adjustable) output voltage version, with an output voltage range of 0.8V to 5.0V. The 1.5A output current capability, combined with the low output voltage capability, make the MCP1727 a good choice for new sub-1.8V output voltage LDO applications that have high current demands. The MCP1727 is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. Only 1 F of output capacitance is needed to stabilize the LDO. Using CMOS construction, the quiescent current consumed by the MCP1727 is typically less than 120 A over the entire input voltage range, making it attractive for portable computing applications that demand high output current. When shut down, the quiescent current is reduced to less than 0.1 A. The scaled-down output voltage is internally monitored and a power good (PWRGD) output is provided when the output is within 92% of regulation (typical). An external capacitor can be used on the CDELAY pin to adjust the delay from 200 s to 300 ms. The overtemperature and short circuit current-limiting provide additional protection for the LDO during system fault conditions. Applications * * * * * * High-Speed Driver Chipset Power Networking Backplane Cards Notebook Computers Network Interface Cards Palmtop Computers 2.5V to 1.XV Regulators Package Types Adjustable (SOIC-8) VIN 1 VIN 2 SHDN 3 GND 4 8 VOUT 7 ADJ 6 CDELAY 5 PWRGD Fixed (SOIC-8) VIN 1 VIN 2 SHDN 3 GND 4 8 VOUT 7 Sense 6 CDELAY 5 PWRGD Adjustable (3x3 DFN) VIN 1 VIN 2 SHDN 3 GND 4 8 7 6 5 VOUT ADJ CDELAY PWRGD Fixed (3x3 DFN) VIN 1 VIN 2 SHDN 3 GND 4 8 7 6 5 VOUT Sense CDELAY PWRGD (c) 2007 Microchip Technology Inc. DS21999B-page 1 MCP1727 Typical Application MCP1727 Fixed Output Voltage VIN = 2.3V to 2.8V C1 4.7 F 1 2 3 4 On Off PWRGD VIN VIN VOUT 8 Sense 7 VOUT = 1.8V @ 1A SHDN CDELAY 6 GND PWRGD 5 C3 1000 pF R1 100 k C2 1 F MCP1727 Adjustable Output Voltage VIN = 2.3V to 2.8V C1 4.7 F VOUT = 1.2V @ 1A R1 40 k 1 2 3 4 VIN VIN VOUT 8 ADJ 7 SHDN CDELAY 6 GND PWRGD 5 C3 1000 pF R3 100 k R2 20 k C2 1 F On Off PWRGD DS21999B-page 2 (c) 2007 Microchip Technology Inc. MCP1727 Functional Block Diagram - Adjustable Output PMOS VIN VOUT Undervoltage Lock Out (UVLO) ISNS Cf Rf ADJ SHDN Overtemperature Sensing Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference + EA - PWRGD CDELAY (c) 2007 Microchip Technology Inc. DS21999B-page 3 MCP1727 Functional Block Diagram - Fixed Output PMOS VIN VOUT Undervoltage Lock Out (UVLO) ISNS Cf Rf Sense SHDN Overtemperature Sensing Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference + EA - PWRGD CDELAY DS21999B-page 4 (c) 2007 Microchip Technology Inc. MCP1727 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VIN ....................................................................................6.5V Maximum Voltage on Any Pin .. (GND - 0.3V) to (VDD + 0.3)V Maximum Power Dissipation......... Internally-Limited (Note 6) Output Short Circuit Duration ................................ Continuous Storage temperature .....................................-65C to +150C Maximum Junction Temperature, TJ ........................... +150C ESD protection on all pins (HBM/MM) ........... 2 kV; 200V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR=1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters Input Operating Voltage Input Quiescent Current Input Quiescent Current for SHDN Mode Maximum Output Current Line Regulation Load Regulation Output Short Circuit Current Sym VIN Iq ISHDN IOUT VOUT/ (VOUT x VIN) VOUT/VOUT IOUT_SC Min 2.3 -- -- 1.5 -- -1.0 -- 120 0.1 -- 0.05 0.5 2.2 Typ Max 6.0 220 3 -- 0.16 1.0 -- Units V A A A %/V % A Note 1 IL = 0 mA, VIN = Note 1, VOUT = 0.8V to 5.0V SHDN = GND VIN = 2.3V to 6.0V VR = 0.8V to 5.0V, Note 1 (Note 1) VIN 6V IOUT = 1 mA to 1.5A, VIN = Note 1, (Note 4) VIN = Note 1, RLOAD < 0.1, Peak Current VIN = 2.3V to VIN = 6.0V, IOUT = 1 mA VIN = 6.0V, VADJ = 0V to 6V Note 3 Note 2 Conditions Adjust Pin Characteristics (Adjustable Output Only) Adjust Pin Reference Voltage Adjust Pin Leakage Current Adjust Temperature Coefficient Voltage Regulation Note 1: 2: 3: 4: 5: 6: VADJ IADJ TCVOUT VOUT 0.402 -10 -- VR - 2.5% 0.410 0.01 40 VR 0.5% 0.418 +10 -- VR + 2.5% V nA ppm/C V Fixed-Output Characteristics (Fixed Output Only) 7: The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150C rating. Sustained junction temperatures above 150C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. (c) 2007 Microchip Technology Inc. DS21999B-page 5 MCP1727 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR=1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters Dropout Characteristics Dropout Voltage Power Good Characteristics PWRGD Input Voltage Operating Range VPWRGD_VIN 1.0 1.2 VPWRGD_TH -- 89 90 PWRGD Threshold Hysteresis PWRGD Output Voltage Low PWRGD Leakage PWRGD Time Delay VPWRGD_HYS VPWRGD_L PWRGD_LK TPG 1.0 -- -- -- -- -- 92 92 2.0 0.2 1 6.0 6.0 -- 95 94 3.0 0.4 -- %VOUT V nA IPWRGD SINK = 1.2 mA, ADJ = 0V, SENSE = 0V VPWRGD = VIN = 6.0V Rising Edge RPULLUP = 10 k -- 10 -- Detect Threshold to PWRGD Active Time Delay Shutdown Input Logic High Input Logic Low Input SHDN Input Leakage Current AC Performance Output Delay From SHDN Note 1: 2: 3: 4: 5: 6: TOR 100 s SHDN = GND to VIN VOUT = GND to 95% VR VSHDN-HIGH VSHDN-LOW SHDNILK -0.1 0.001 45 15 +0.1 %VIN %VIN A VIN = 2.3V to 6.0V VIN = 2.3V to 6.0V VIN = 6V, SHDN =VIN, SHDN = GND TVDET-PWRGD -- 200 30 300 200 -- 55 -- -- s ms ms s CDELAY = OPEN CDELAY = 0.01 F CDELAY = 0.1 F VADJ or VSENSE = VPWRGD_TH + 20 mV to VPWRGD_TH - 20 mV %VOUT V TA = +25C TA = -40C to +125C For VIN < 2.3V, ISINK = 100 A PWRGD Threshold Voltage (Referenced to VOUT) Falling Edge VOUT < 2.5V Fixed, VOUT = Adj. VOUT >= 2.5V Fixed VIN-VOUT -- 330 550 mV Note 5, IOUT = 1.5A, VIN(MIN) = 2.3V Sym Min Typ Max Units Conditions ICDELAY = 140 nA (Typ) 7: The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150C rating. Sustained junction temperatures above 150C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. DS21999B-page 6 (c) 2007 Microchip Technology Inc. MCP1727 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR=1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 F (X7R Ceramic), TA = +25C. Boldface type applies for junction temperatures, TJ (Note 7) of -40C to +125C Parameters Output Noise Sym eN Min -- Typ 2.0 Max -- Units V/Hz Conditions IOUT = 200 mA, f = 1 kHz, COUT = 10 F (X7R Ceramic), VOUT = 2.5V f = 100 Hz, COUT = 10 F, IOUT = 10 mA, VINAC = 30 mV pk-pk, CIN = 0 F IOUT = 100 A, VOUT = 1.8V, VIN = 2.8V IOUT = 100 A, VOUT = 1.8V, VIN = 2.8V Power Supply Ripple Rejection Ratio PSRR -- 60 -- dB Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: 2: 3: 4: 5: 6: TSD TSD -- -- 150 10 -- -- C C 7: The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH - VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150C rating. Sustained junction temperatures above 150C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits apply for VIN = 2.3V to 6.0V. Parameters Temperature Ranges Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8LD 3x3 DFN JA -- 41 -- C/W 4-Layer JC51-7 Standard Board with vias 4-Layer JC51-7 Standard Board TJ TJ TA -40 -- -65 -- -- -- +125 +150 +150 C C C Steady State Transient Sym Min Typ Max Units Conditions Thermal Resistance, 8LD SOIC JA -- 150 -- C/W (c) 2007 Microchip Technology Inc. DS21999B-page 7 MCP1727 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 F Ceramic (X7R), CIN = 4.7 F Ceramic (X7R), IOUT = 1 mA, Temperature = +25C, VIN = VOUT + 0.6V, RPWRGD = 10 k To VIN. NOTE: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired Junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant. 150 Quiescent Current (A) 140 130 120 110 100 90 2 3 4 Input Voltage (V) 5 6 130C 90C 25C -45C VOUT = 1.2V Adj IOUT = 0 mA 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 Line Regulation (%/V) VOUT = 1.2V adj VIN = 2.3V to 6.0V IOUT = 1 mA IOUT = 1000 mA IOUT = 100 mA IOUT = 500 mA -45 -20 5 30 55 80 105 130 Temperature (C) FIGURE 2-1: Quiescent Current vs. Input Voltage (1.2V Adjustable). 200 190 180 170 160 150 140 130 120 110 100 0 FIGURE 2-4: Line Regulation vs. Temperature (1.2V Adjustable). 0.15 VOUT = 1.2V Adj VIN=5.0V Ground Current (A) Load Regulation (%) 0.10 0.05 0.00 -0.05 -0.10 -0.15 VOUT = 3.3V IOUT = 1.0 mA to 1500 mA VOUT = 0.8V VOUT = 5.0V VOUT = 1.8V VIN=3.3V VIN=2.3V 250 500 750 1000 1250 1500 -45 -20 5 30 55 80 105 130 Load Current (mA) Temperature (C) FIGURE 2-2: Ground Current vs. Load Current (1.2V Adjustable). 140 Quiescent Current (A) 135 130 125 120 115 110 105 100 -45 -20 5 30 55 80 105 130 Temperature (C) VIN=5.0V VIN=4.0V VIN=2.5V FIGURE 2-5: Temperature. 0.411 Adjust Pin Voltage (V) 0.410 0.410 0.409 0.409 Load Regulation vs. IOUT = 0 mA VOUT = 1.2V Adj VIN = 6.0V VIN = 5.0V VIN = 2.3V IOUT = 1.0 mA 0.408 -45 -20 5 30 55 80 105 130 Temperature (C) FIGURE 2-3: Quiescent Current vs. Junction Temperature (1.2V Adjustable). DS21999B-page 8 FIGURE 2-6: Temperature. Adjust Pin Voltage vs. (c) 2007 Microchip Technology Inc. MCP1727 NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 F Ceramic (X7R), CIN = 4.7 F Ceramic (X7R), IOUT = 1 mA, Temperature = +25C, VIN = VOUT + 0.6V, RPWRGD = 10 k To VIN. 0.35 Dropout Voltage (V) 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 250 500 750 1000 1250 1500 Load Current (mA) VOUT = 2.5V Adj VOUT = 5.0V Adj 150 Quiescent Current (A) 140 130 120 110 100 90 80 2 VOUT = 0.8V IOUT = 0 mA +130C +85C +25C -45C 3 4 Input Voltage (V) 5 6 FIGURE 2-7: Dropout Voltage vs. Load Current (Adjustable Version). 0.42 Dropout Voltage (V) 0.40 0.38 0.36 0.34 0.32 0.30 -45 -20 5 30 55 80 105 130 Temperature (C) VOUT = 3.3V Adj VOUT = 2.5V Adj VOUT = 5.0V Adj FIGURE 2-10: Quiescent Current vs. Input Voltage (0.8V Fixed). 150 Quiescent Current (A) 140 130 120 110 100 90 80 3 3.5 4 4.5 5 5.5 6 Input Voltage (V) -45C IOUT = 1.5A VOUT = 2.5V IOUT = 0 mA +130C +90C +25C FIGURE 2-8: Dropout Voltage vs. Temperature (Adjustable Version). 32 Power Good Time Delay (mS) 31 30 29 28 27 26 25 -45 -20 5 30 55 80 105 130 Temperature (C) VIN = 3.3V VIN = 5.0V VIN = 2.4V FIGURE 2-11: Quiescent Current vs. Input Voltage (2.5V Fixed). 250.00 Ground Current (A) 200.00 VOUT=0.8V CDELAY = 0.01 F VOUT = 1.8V Adj 150.00 100.00 50.00 0.00 0 250 500 750 1000 1250 1500 Load Current (mA) VOUT=2.5V VIN = 2.3V for VR=0.8V VIN = 3.1V for VR=2.5V FIGURE 2-9: Power Good (PWRGD) Time Delay vs. Temperature. FIGURE 2-12: Current. Ground Current vs. Load (c) 2007 Microchip Technology Inc. DS21999B-page 9 MCP1727 NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 F Ceramic (X7R), CIN = 4.7 F Ceramic (X7R), IOUT = 1 mA, Temperature = +25C, VIN = VOUT + 0.6V, RPWRGD = 10 k To VIN. 130 Quiescent Current (A) 125 120 115 110 105 100 95 -45 VOUT = 0.8V IOUT = 0 mA 0.045 Line Regulation (%/V) 0.040 IOUT = 1 mA VR = 2.5V VIN = 3.1 to 6.0V 0.035 0.030 0.025 0.020 0.015 IOUT = 1500 mA IOUT = 100 mA IOUT = 1000 mA IOUT = 500 mA VOUT = 2.5V -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (C) Temperature (C) FIGURE 2-13: Temperature. 0.30 0.25 Ishdn (A) 0.20 0.15 0.10 0.05 0.00 -45 -20 5 Quiescent Current vs. FIGURE 2-16: Line Regulation vs. Temperature (2.5V Fixed). VR = 0.8V 0.30 Load Regulation (%) 0.20 0.10 0.00 -0.10 -0.20 -0.30 -45 -20 5 30 55 80 IOUT = 1 mA to 1500 mA VOUT = 0.8V VIN = 2.3V VIN = 6.0V VIN = 4.0V VIN = 2.3V 30 55 80 105 130 105 130 Temperature (C) Temperature (C) FIGURE 2-14: ISHDN vs. Temperature. FIGURE 2-17: Load Regulation vs. Temperature (VOUT < 2.5V Fixed). 0.00 -0.05 Load Regulation (%) 0.10 Line Regulation (%/V) 0.08 0.06 0.04 0.02 0.00 -45 -20 5 30 55 80 105 130 Temperature (C) IOUT = 1A IOUT = 100 mA IOUT = 500mA VOUT = 0.8V VIN = 2.3V to 6.0V IOUT = 1 mA IOUT = 1 mA to 1500 mA VOUT = 2.5V -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -45 VOUT = 5.0V -20 5 30 55 80 105 130 Temperature (C) FIGURE 2-15: Line Regulation vs. Temperature (0.8V Fixed). FIGURE 2-18: Load Regulation vs. Temperature (VOUT 2.5V Fixed). DS21999B-page 10 (c) 2007 Microchip Technology Inc. MCP1727 NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 F Ceramic (X7R), CIN = 4.7 F Ceramic (X7R), IOUT = 1 mA, Temperature = +25C, VIN = VOUT + 0.6V, RPWRGD = 10 k To VIN. 0.40 0.35 Dropout Voltage (V) 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 250 500 750 1000 1250 1500 Load Current (mA) VOUT = 5.0V Temperature = 25C VOUT = 2.5V 10 VR=2.5V, VIN=3.3V COUT=1 F ceramic X7R CIN=10 F ceramic Noise (V/ Hz) 1 0.1 0.01 0.001 0.01 VR=0.8V, VIN=2.3V IOUT=200 mA 0.1 1 10 Frequency (kHz) 100 1000 FIGURE 2-19: Current. 0.45 Dropout Voltage (V) 0.40 Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage Density vs. Frequency. 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 0.01 VR=1.2V Adj COUT=10 F ceramic X7R VIN=3.1V CIN=0 F IOUT=10 mA IOUT = 1.5A 0.35 0.30 VOUT = 5.0V VOUT = 2.5V 0.25 -45 -20 5 30 55 80 105 130 Temperature (C) 0.1 1 10 Frequency (kHz) 100 1000 FIGURE 2-20: Temperature. Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 1.2V Adj.). 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 0.01 0.1 VR=1.2V Adj COUT=22 F ceramic X7R VIN=3.1V CIN=0 F IOUT=10 mA 3.00 Short Circuit Current (A) 2.50 2.00 1.50 1.00 0.50 0.00 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Voltage (V) VOUT = 2.5V Temperature = 25C 1 10 Frequency (kHz) 100 1000 FIGURE 2-21: Input Voltage. Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 1.2V Adj.). (c) 2007 Microchip Technology Inc. DS21999B-page 11 MCP1727 NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 F Ceramic (X7R), CIN = 4.7 F Ceramic (X7R), IOUT = 1 mA, Temperature = +25C, VIN = VOUT + 0.6V, RPWRGD = 10 k To VIN. 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 0.01 0.1 VR=2.5V Fixed COUT=10 F ceramic X7R VIN=3.3V CIN=0 F IOUT=10 mA 1 10 Frequency (kHz) 100 1000 FIGURE 2-25: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 2.5V Fixed). 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0.01 FIGURE 2-28: Shutdown. 2.5V (Fixed) Startup from PSRR (dB) VR=2.5V Fixed COUT=22 F ceramic X7R VIN=3.3V CIN=0 F IOUT=10 mA 0.1 1 10 Frequency (kHz) 100 1000 FIGURE 2-26: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 2.5V Fixed). FIGURE 2-29: Power Good (PWRGD) Timing with CBYPASS of 1000 pF. FIGURE 2-27: VIN. 2.5V (Fixed) Startup from FIGURE 2-30: Power Good (PWRGD) Timing with CBYPASS of 0.1 F. DS21999B-page 12 (c) 2007 Microchip Technology Inc. MCP1727 NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 F Ceramic (X7R), CIN = 4.7 F Ceramic (X7R), IOUT = 1 mA, Temperature = +25C, VIN = VOUT + 0.6V, RPWRGD = 10 k To VIN. FIGURE 2-31: (0.8V Fixed). Dynamic Line Response FIGURE 2-33: Dynamic Load Response (2.5V Fixed, 10 mA to 1000 mA). FIGURE 2-32: (2.5V Fixed). Dynamic Line Response FIGURE 2-34: Dynamic Load Response (2.5V Fixed, 100 mA to 1000 mA). (c) 2007 Microchip Technology Inc. DS21999B-page 13 MCP1727 3.0 PIN DESCRIPTION PIN FUNCTION TABLE Adjustable Output 1 2 3 4 5 6 7 -- The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Fixed Output 1 2 3 4 5 6 -- Name VIN VIN SHDN GND PWRGD CDELAY ADJ Sense VOUT EP Description Input Voltage Supply Input Voltage Supply Shutdown Control Input (active-low) Ground Power Good Output (open-drain) Power Good Delay Set-Point Input Voltage Sense Input (adjustable version) Voltage Sense Input (fixed voltage version) Regulated Output Voltage Exposed Pad of the DFN Package (ground potential) 7 8 Exposed Pad 8 Exposed Pad 3.1 Input Voltage Supply (VIN) 3.4 Power Good Output (PWRGD) Connect the unregulated or regulated input voltage source to VIN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 1 F to 10 F should be sufficient for most applications. 3.2 Shutdown Control Input (SHDN) The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the PWRGD output also goes low and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.1 A. The PWRGD output is an open-drain output used to indicate when the LDO output voltage is within 92% (typically) of its nominal regulation value. The PWRGD threshold has a typical hysteresis value of 2%. The PWRGD output is typically delayed by 200 s (typical, no capacitance on CDELAY pin) from the time the LDO output is within 92% + 3% (max hysteresis) of the regulated output value on power-up. This delay time is controlled by the CDELAY pin. 3.5 Power Good Delay Set-Point Input (CDELAY) 3.3 Ground (GND) The CDELAY input sets the power-up delay time for the PWRGD output. By connecting an external capacitor from the CDELAY pin to ground, the typical delay times for the PWRGD output can be adjusted from 200 s (no capacitance) to 300 ms (0.1 F capacitor). This allows for the optimal setting of the system reset time. Connect the GND pin of the LDO to a quiet circuit ground. This will help the LDO power supply rejection ratio and noise performance. The ground pin of the LDO only conducts the quiescent current of the LDO (typically 120 A), so a heavy trace is not required. For applications have switching or noisy inputs tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 3.6 3.6.1 Output Voltage Sense/Adjust Input (ADJ/Sense) ADJ For adjustable applications, the output voltage is connected to the ADJ input through a resistor divider that sets the output voltage regulation value. This provides the user the capability to set the output voltage to any value they desire within the 0.8V to 5.0V range of the device. DS21999B-page 14 (c) 2007 Microchip Technology Inc. MCP1727 3.6.2 Sense 3.7 Regulated Output Voltage (VOUT) For fixed output voltage versions of the device, the SENSE input is used to provide output voltage feedback to the internal circuitry of the MCP1727. The SENSE pin typically improves load regulation by allowing the device to compensate for voltage drops due to packaging and circuit board layout. The VOUT pin(s) is the regulated output voltage of the LDO. A minimum output capacitance of 1.0 F is required for LDO stability. The MCP1727 is stable with ceramic, tantalum and aluminum-electrolytic capacitors. See Section 4.3 "Output Capacitor" for output capacitor selection guidance. 3.8 Exposed Pad (EP) The 3x3 DFN package has an exposed pad on the bottom of the package. This pad should be soldered to the Printed Circuit Board (PCB) to aid in the removal of heat from the package during operation. The exposed pad is at the ground potential of the LDO. (c) 2007 Microchip Technology Inc. DS21999B-page 15 MCP1727 4.0 DEVICE OVERVIEW EQUATION 4-2: V OUT - V ADJ R 1 = R 2 -------------------------------- V ADJ = = LDO Output Voltage ADJ Pin Voltage (typically 0.41V) The MCP1727 is a high output current, Low Dropout (LDO) voltage regulator with an adjustable delay power-good output and shutdown control input. The low dropout voltage of 330 mV typical at 1.5A of current makes it ideal for battery-powered applications. Unlike other high output current LDOs, the MCP1727 only draws a maximum of 220 A of quiescent current. Where: VOUT VADJ 4.1 LDO Output Voltage 4.2 The MCP1727 LDO is available with either a fixed output voltage or an adjustable output voltage. The output voltage range is 0.8V to 5.0V for both versions. Output Current and Current Limiting 4.1.1 ADJUST INPUT The adjustable version of the MCP1727 uses the ADJ pin (pin 7) to get the output voltage feedback for output voltage regulation. This allows the user to set the output voltage of the device with two external resistors. The nominal voltage for ADJ is 0.41V. Figure 4-1 shows the adjustable version of the MCP1727. Resistors R1 and R2 form the resistor divider network necessary to set the output voltage. With this configuration, the equation for setting VOUT is: The MCP1727 LDO is tested and ensured to supply a minimum of 1.5A of output current. The MCP1727 has no minimum output load, so the output load current can go to 0 mA and the LDO will continue to regulate the output voltage to within tolerance. The MCP1727 also incorporates an output current limit. If the output voltage falls below 0.7V due to an overload condition (usually represents a shorted load condition), the output current is limited to 2.2A (typical). If the overload condition is a soft overload, the MCP1727 will supply higher load currents of up to 3A. The MCP1727 should not be operated in this condition continuously as it may result in failure of the device. However, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 1.5A or less. Output overload conditions may also result in an overtemperature shutdown of the device. If the junction temperature rises above 150C, the LDO will shut down the output voltage. See Section 4.9 "Overtemperature Protection" for more information on overtemperature shutdown. EQUATION 4-1: R1 + R2 V OUT = V ADJ ------------------ R2 = = LDO Output Voltage ADJ Pin Voltage (typically 0.41V) Where: VOUT VADJ 4.3 MCP1727-ADJ VIN C1 4.7 F On Off 1 VIN 2 VIN 4 GND VOUT 8 ADJ 7 Output Capacitor VOUT R1 C2 1 F 3 SHDN CDELAY 6 PWRGD 5 The MCP1727 requires a minimum output capacitance of 1 F for output voltage stability. Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series Resistance (ESR) of the electrolytic output capacitor must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 F X7R 0805 capacitor has an ESR of 50 milli-ohms. Larger LDO output capacitors can be used with the MCP1727 to improve dynamic performance and power supply ripple rejection performance. A maximum of 22 F is recommended. Aluminum-electrolytic capacitors are not recommended for low-temperature applications of 25C. C3 1000 pF R2 FIGURE 4-1: Typical adjustable output voltage application circuit. The allowable resistance value range for resistor R2 is from 10 k to 200 k. Solving the equation for R1 yields the following equation: DS21999B-page 16 (c) 2007 Microchip Technology Inc. MCP1727 4.4 Input Capacitor Low input source impedance is necessary for the LDO output to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 F to 4.7 F is recommended for most applications. For applications that have output step load requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO with a good local low-impedance source to pull the transient currents from in order to respond quickly to the output load step. For good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO. The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking 1.2 mA (VPWRGD < 0.4V maximum). VPWRGD_TH VOUT TPG VOH TVDET_PWRGD PWRGD VOL FIGURE 4-2: Power Good Timing. 4.5 Power Good Output (PWRGD) VIN TOR 70 s The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see Section 1.0 "Electrical Characteristics" for Minimum and Maximum specifications) of its nominal regulation value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as TPG in the Electrical Characteristics table). The power good time delay is adjustable via the CDELAY pin of the LDO (see Section 4.6 "CDELAY Input"). By placing a capacitor from the CDELAY pin to ground, the power good time delay can be adjusted from 200 s (no capacitance) to 300 ms (0.1 F capacitor). After the time delay period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power good threshold, the power good output will transition low. The power good circuitry has a 170 s delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See Figure 4-2 for power good timing characteristics. When the LDO is put into Shutdown mode using the SHDN input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. The timing diagram for the power good output when using the shutdown input is shown in Figure 4-3. 30 s SHDN TPG VOUT PWRGD FIGURE 4-3: Shutdown. Power Good Timing from 4.6 CDELAY Input The CDELAY input is used to provide the power-up delay timing for the power good output, as discussed in the previous section. By adding a capacitor from the CDELAY pin to ground, the PWRGD power-up time delay can be adjusted from 200 s (no capacitance on CDELAY) to 300 ms (0.1 F of capacitance on CDELAY). See Section 1.0 "Electrical Characteristics" for CDELAY timing tolerances. (c) 2007 Microchip Technology Inc. DS21999B-page 17 MCP1727 Once the power good threshold (rising) has been reached, the CDELAY pin charges the external capacitor to VIN. The charging current is 140 nA (typical). The PWRGD output will transition high when the CDELAY pin voltage has charged to 0.42V. If the output falls below the power good threshold limit during the charging time between 0.0V and 0.42V on the CDELAY pin, the CDELAY pin voltage will be pulled to ground, thus resetting the timer. The CDELAY pin will be held low until the output voltage of the LDO has once again risen above the power good rising threshold. A timing diagram showing CDELAY, PWRGD and VOUT is shown in Figure 4-4. high (turn-on) to the LDO output being in regulation is typically 100 s. See Figure 4-5 for a timing diagram of the SHDN input. TOR 400 ns (typ) 30 s SHDN 70 s VOUT VOUT VPWRGD_TH FIGURE 4-5: Diagram. TPG 0V CDELAY VIN (typ) Shutdown Input Timing 4.8 CDELAY Threshold (0.42V) Dropout Voltage and Undervoltage Lockout PWRGD FIGURE 4-4: Diagram. CDELAY and PWRGD Timing Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a VR + 0.6V differential applied. The MCP1727 LDO has a very low dropout voltage specification of 330 mV (typical) at 1.5A of output current. See Section 1.0 "Electrical Characteristics" for maximum dropout voltage specifications. The MCP1727 LDO operates across an input voltage range of 2.3V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the LDO output voltage off until the input voltage reaches a minimum of 2.18V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output will remain on until the input voltage level reaches 2.04V (typical). Since the MCP1727 LDO undervoltage lockout activates at 2.04V as the input voltage is falling, the dropout voltage specification does not apply for output voltages that are less than 1.9V. For high-current applications, voltage drops across the PCB traces must be taken into account. The trace resistances can cause significant voltage drops between the input voltage source and the LDO. For applications with input voltages near 2.3V, these PCB trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout. 4.7 Shutdown Input (SHDN) The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a percentage of the input voltage. The typical value of this shutdown threshold is 30% of VIN, with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. The SHDN input will ignore low-going pulses (pulses meant to shut down the LDO) that are up to 400 ns in pulse width. If the shutdown input is pulled low for more than 400 ns, the LDO will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the shutdown input signal. On the rising edge of the SHDN input, the shutdown circuitry has a 30 s delay before allowing the LDO output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the 30 s delay, the LDO output enters its soft-start period as it rises from 0V to its final regulation value. If the SHDN input signal is pulled low during the 30 s delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going DS21999B-page 18 (c) 2007 Microchip Technology Inc. MCP1727 4.9 Overtemperature Protection The MCP1727 LDO has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately 150C. If the LDO junction temperature does reach 150C, the LDO output will be turned off until the junction temperature cools to approximately 140C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section 5.0 "Application Circuits/Issues" for more information on LDO power dissipation and junction temperature. (c) 2007 Microchip Technology Inc. DS21999B-page 19 MCP1727 5.0 5.1 APPLICATION CIRCUITS/ ISSUES Typical Application In addition to the LDO pass element power dissipation, there is power dissipation within the MCP1727 as a result of quiescent or ground current. The power dissipation as a result of the ground current can be calculated using the following equation: The MCP1727 is used for applications that require high LDO output current and a power good output. MCP1727-2.5 VIN = 3.3V C1 10 F On Off 1 VIN 2 VIN VOUT 8 Sense 7 VOUT = 2.5V @ 1.5A R1 10k EQUATION 5-2: P I ( GND ) = V IN ( MAX ) x I VIN Where: PI(GND VIN(MAX) IVIN = = = Power dissipation due to the quiescent current of the LDO Maximum input voltage Current flowing in the VIN pin with no LDO output current (LDO quiescent current) 3 SHDN CDELAY 6 4 GND PWRGD 5 C2 10 F C3 1000 pF PWRGD FIGURE 5-1: 5.1.1 Typical Application Circuit. APPLICATION CONDITIONS Package Type = 3x3DFN8 The total power dissipated within the MCP1727 is the sum of the power dissipated in the LDO pass device and the P(IGND) term. Because of the CMOS construction, the typical IGND for the MCP1727 is 120 A. Operating at a maximum of 3.465V results in a power dissipation of 0.49 milli-Watts. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the MCP1727 is +125C. To estimate the internal junction temperature of the MCP1727, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RJA) of the device. The thermal resistance from junction to ambient for the 3x3 DFN package is estimated at 41 C/W. Input Voltage Range = 3.3V 5% VIN maximum = 3.465V VIN minimum = 3.135V VDROPOUT (max) = 0.525V VOUT (typical) = 2.5V IOUT = 1.5A maximum PDISS (typical) = 1.2W Temperature Rise = 49.2C EQUATION 5-3: T J ( MAX ) = P TOTAL x R JA + T AMAX TJ(MAX) = Maximum continuous junction temperature PTOTAL = Total device power dissipation RJA = Thermal resistance from junction to ambient TAMAX = Maximum ambient temperature 5.2 5.2.1 Power Calculations POWER DISSIPATION The internal power dissipation within the MCP1727 is a function of input voltage, output voltage, output current and quiescent current. Equation 5-1 can be used to calculate the internal power dissipation for the LDO. EQUATION 5-1: P LDO = ( V IN ( MAX ) ) - V OUT ( MIN ) ) x I OUT ( MAX ) ) Where: PLDO VIN(MAX) VOUT(MIN) = = = LDO Pass device internal power dissipation Maximum input voltage LDO minimum output voltage DS21999B-page 20 (c) 2007 Microchip Technology Inc. MCP1727 The maximum power dissipation capability for a package can be calculated given the junction-toambient thermal resistance and the maximum ambient temperature for the application. Equation 5-4 can be used to determine the package maximum internal power dissipation. 5.3 Typical Application Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation is calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected. EQUATION 5-4: P D ( MAX ) ( T J ( MAX ) - T A ( MAX ) ) = --------------------------------------------------R JA 5.3.1 Package POWER DISSIPATION EXAMPLE PD(MAX) = Maximum device power dissipation TJ(MAX) = maximum continuous junction temperature TA(MAX) = maximum ambient temperature RJA = Thermal resistance from junction to ambient Package Type = 3x3DFN Input Voltage VIN = 3.3V 5% LDO Output Voltage and Current VOUT = 2.5V IOUT = 1.5A Maximum Ambient Temperature TA(MAX) = 60C Internal Power Dissipation PLDO(MAX) = (VIN(MAX) - VOUT(MIN)) x IOUT(MAX) PLDO = ((3.3V x 1.05) - (2.5V x 0.975)) x 1.5A PLDO = 1.54 Watts EQUATION 5-5: T J ( RISE ) = P D ( MAX ) x R JA TJ(RISE) = Rise in device junction temperature over the ambient temperature PD(MAX) = Maximum device power dissipation RJA = Thermal resistance from junction to ambient 5.3.1.1 Device Junction Temperature Rise EQUATION 5-6: T J = T J ( RISE ) + T A TJ = Junction temperature TJ(RISE) = Rise in device junction temperature over the ambient temperature TA = Ambient temperature The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (RJA) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface-mount packages. The EIA/JEDEC specification is JESD51-7 "High Effective Thermal Conductivity Test Board for Leaded Surface-Mount Packages". The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792, "A Method to Determine How Much Power a SOT23 Can Dissipate in an Application" (DS00792), for more information regarding this subject. TJ(RISE) = PTOTAL x RJA TJRISE = 1.54 W x 41.0 C/W TJRISE = 63.14C (c) 2007 Microchip Technology Inc. DS21999B-page 21 MCP1727 5.3.1.2 Junction Temperature Estimate 5.4 CDELAY Calculations (typical) T C = I * -----V To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: TJ = TJRISE + TA(MAX) TJ = 63.14C + 60.0C TJ = 123.14C As you can see from the result, this application will be operating very near the maximum operating junction temperature of 125C. The PCB layout for this application is very important as it has a significant impact on the junction-to-ambient thermal resistance (RJA) of the 3x3 DFN package, which is very important in this application. Where: C I T V = = = = CDELAY Capacitor CDELAY charging current, 140 nA typical. time delay CDELAY threshold voltage, 0.42V typical - 09 T ( 140nA * T ) C = I * ------ = --------------------------------- = 333.3 x10 * T V 0.42V For a delay of 300 ms: C = 333.3E-09 * .300 C = 100E-09uF (0.1 F) 5.3.1.3 Maximum Package Power Dissipation at 60C Ambient Temperature 3x3DFN (41 C/W RJA): PD(MAX) = (125C - 60C) / 41 C/W PD(MAX) = 1.585W SOIC8 (150C/Watt RJA): PD(MAX) = (125C - 60C)/ 150 C/W PD(MAX) = 0.433W From this table, you can see the difference in maximum allowable power dissipation between the 3x3 DFN package and the 8-pin SOIC package. This difference is due to the exposed metal tab on the bottom of the DFN package. The exposed tab of the DFN package provides a very good thermal path from the die of the LDO to the PCB. The PCB then acts like a heatsink, providing more area to distribute the heat generated by the LDO. DS21999B-page 22 (c) 2007 Microchip Technology Inc. MCP1727 6.0 6.1 PACKAGING INFORMATION Package Marking Information 8-Lead DFN (3x3) XXXX YYWW NNN Standard Extended Temp Code Voltage Options * Code Voltage Options * Example: CAAJ 0620 256 CAAJ 0.8 CAAP 3.0 CAAK 1.2 CAAQ 3.3 CAAL 1.8 CAAR 5.0 CAAM 2.5 CAAH ADJ * Custom output voltages available upon request. Contact your local Microchip sales office for more information. 8-Lead SOIC (150 mil) Standard Extended Temp Example: XXXXXXXX XXXXYYWW NNN Code Voltage Options * Code Voltage Options * 082E 0.8 302E 3.0 122E 1.2 332E 3.3 182E 1.8 502E 5.0 252E 2.5 ADJE ADJ * Custom output voltages available upon request. Contact your local Microchip sales office for more information. 1727082E SN e3 ^^0620 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. DS21999B-page 23 MCP1727 8-Lead Plastic Dual Flat, No Lead Package (MF) - 3x3x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e N L EXPOSED PAD E K NOTE 1 1 2 D2 TOP VIEW 2 1 NOTE 1 E2 D N b BOTTOM VIEW A NOTE 2 A3 A1 Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length Exposed Pad Width Overall Width Exposed Pad Length Contact Width Contact Length N e A A1 A3 D E2 E D2 b L 0.00 0.25 0.20 0.00 0.80 0.00 MIN MILLIMETERS NOM 8 0.65 BSC 0.90 0.02 0.20 REF 3.00 BSC - 3.00 BSC - 0.30 0.30 2.40 0.35 0.55 - 1.60 1.00 0.05 MAX Contact-to-Exposed Pad K 0.20 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-062B DS21999B-page 24 (c) 2007 Microchip Technology Inc. MCP1727 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 b h c h A A2 A1 L L1 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 5 0.25 0.40 - 1.25 0.10 MIN MILLMETERS NOM 8 1.27 BSC - - - 6.00 BSC 3.90 BSC 4.90 BSC - - 1.04 REF - - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX 15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B (c) 2007 Microchip Technology Inc. DS21999B-page 25 MCP1727 NOTES: DS21999B-page 26 (c) 2007 Microchip Technology Inc. MCP1727 APPENDIX A: REVISION HISTORY Revision B (February 2007) * * * * Revised Notes on pages 8-13. Added junction temperature note. Figure 2-22: Revised label on Y-axis Figure 2-27 and Figure 2-28: Replaced figure and revised figure captions. * Added disclaimers to package outline drawings. * Updated package outline drawings. Revision A (July 2006) * Original Release of this Document. (c) 2007 Microchip Technology Inc. DS21999B-page 27 MCP1727 NOTES: DS21999B-page 28 (c) 2007 Microchip Technology Inc. MCP1727 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XX X X X/ XX Examples: a) MCP1727-0802E/MF: 0.8V Low Dropout Regulator, DFN8 pkg. Output Feature Tolerance Temp. Package Voltage Code b) Device: MCP1727: 1.5A Low Dropout Regulator MCP1727T: 1.5A Low Dropout Regulator Tape and Reel MCP1727T-1202E/MF: Tape and Reel, 1.2V Low Dropout Regulator, DFN8 pkg. MCP1727-1802E/MF: 1.8V Low Dropout Voltage Regulator, DFN8 pkg. c) Output Voltage *: 08 12 18 25 30 33 50 = = = = = = = 0.8V "Standard" 1.2V "Standard" 1.8V "Standard" 2.5V "Standard" 3.0V "Standard" 3.3V "Standard" 5.0V "Standard" d) MCP1727T-2502E/MF: Tape and Reel, 2.5V Low Dropout Voltage Regulator, DFN8 pkg. MCP1727-3002E/MF: 3.0V Low Dropout Voltage Regulator, DFN8 pkg. 3.3V Low Dropout Voltage Regulator, DFN8 pkg. *Contact factory for other output voltage options Extra Feature Code: Tolerance: Temperature: Package Type: 0 2 E = Fixed = 2.0% (Standard) e) f) MCP1727-3302E/MF: g) = -40C to +125C MCP1727T-5002E/MF: Tape and Reel, 5.0V Low Dropout Voltage Regulator, DFN8 pkg. MCP1727T-0802E/SN: Tape and Reel, 0.8V Low Dropout Voltage Regulator, SOIC8 pkg. MCP1727-1202E/SN: 1.2V Low Dropout Voltage Regulator, SOIC8 pkg. MF = Plastic Dual Flat No Lead (DFN) (3x3x0.9 mm Body), 8-lead SN = Plastic Small Outline (150 mil Body), 8-lead h) i) j) MCP1727T-1802E/SN: Tape and Reel, 1.8V Low Dropout Voltage Regulator, SOIC8 pkg. MCP1727-2502E/SN: 2.5V Low Dropout Voltage Regulator, SOIC8 pkg. 3.0V Low Dropout Voltage Regulator, SOIC8 pkg. 3.3V Low Dropout Voltage Regulator, SOIC8 pkg. k) l) MCP1727-3002E/SN: m) MCP1727-3302E/SN: n) MCP1727T-5002E/SN: Tape and Reel, 5.0V Low Dropout Voltage Regulator, SOIC8 pkg. (c) 2007 Microchip Technology Inc. DS21999B-page 29 MCP1727 NOTES: DS21999B-page 30 (c) 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. 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